In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form circuits. Interconnection of these devices within an integrated circuit is typically accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching contact openings such as vias. A second pattern and etch defines trenches, the wiring between vias. Conductive material, such as copper is then deposited into the vias and trenches to form the next level of interconnect. Dielectric material is then deposited over the patterned conductive layer, and the process may be repeated any number of times using additional wiring levels laid out over additional dielectric layers with conductive vias therebetween to form the multi-level interconnect network.
As device densities and operational speeds continue to increase and transistor scaling proceeds into the deep sub-micron regime, reduction of the RC delay times in integrated circuits is desired. These delays may be related to stray parasitic capacitances between adjacent metal lines and/or semiconductor components as well as the resistance of interconnect metal lines through the multi-layer interconnect networks. Some integrated circuits and integrated circuit devices are particularly sensitive to stray capacitances and noise, such as those components at the inputs of operational amplifiers and other similar high input impedance or high gain circuits, high speed switching circuits, or radio frequency (RF) integrated circuits.
A planar capacitor, for example, is a component that is affected in this way by stray capacitive coupling and noise. Accordingly, the structure of some conventional integrated capacitors is such that they tend to receive coupling from various metal lines, semiconductor components and noise sources. Several conventional integrated circuit capacitors have been proposed that are in the proximity of the semiconductor substrate and may have a shield layer between the capacitor and the substrate. At least one conventional approach uses a plate of the capacitor also as the shield, requiring that the shield-plate be grounded or otherwise connected to a “quiet voltage”. In these approaches, however, the usefulness of the capacitor may be somewhat limited to those circuit applications where one plate potential can be fixed or predetermined. Another prior art integrated capacitor uses multiple capacitors that are interconnected in a custom arrangement that tends to limit use to specific application configurations.
The measure of the quality factor, or “Q” of a capacitor is another parameter that is particularly important for low-loss capacitors used in RF circuits and various other high-speed circuits. Some existing integrated capacitor designs have a solid conductive plate or shield layer. Such solid conductive layers may tend to develop eddy currents within the plates that needlessly consume power and degrade the Q of the capacitor. In addition, stray capacitances, internal and external circuit noise, EMI, and RFI generally tend to produce unpredictable circuit performance in an unshielded, or inadequately shielded capacitor.
Accordingly, it is desirable to fabricate a planar capacitor integrated within a semiconductor device sufficiently shielded from noise to provide more predictable capacitance performance and circuit design parameters that may be employed to increase speed, reduce cross-talk, and to limit power consumption in modern high-speed, high-density devices.